mustangyhz
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Posts: 37
china
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plltop: vco #(.f0(1.5E9), .kvco(50.0E6), .rin(100k))
module vco (out, ps, ns); parameter real f0 = 100k; parameter real kvco = 10k; parameter real rin= 100k from (0:inf); output out; electrical ps, ns; reg out; logic out; real vin; initial out = 0; always begin vin = V(ps, ns); # (0.5e9 / (f0 + kvco * vin)) out = ~out; end
analog I(ps, ns) <+ V(ps,ns)/rin; endmodule
dose it mean: 1, f0=1.5E9 2, out = ~out after every (0.5e9 / (f0 + kvco * vin)) then the period of signal out is about 666ms, I think it should be 666ps. I delete 'e9' ,and I got the wrong answer. why?
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