plltop:
vco #(.f0(1.5E9), .kvco(50.0E6), .rin(100k))

module vco (out, ps, ns);
   parameter real f0 = 100k;                            parameter real kvco = 10k;      
   parameter real rin= 100k from (0:inf);            
   output out;
   electrical ps, ns;
   reg out;
   logic out;
   real vin;
   initial out = 0;      
   always begin
     vin = V(ps, ns);            
# (0.5e9 / (f0 + kvco * vin))            
     out = ~out;                                  end

   analog I(ps, ns) <+ V(ps,ns)/rin;      
endmodule

dose it mean:
1,    f0=1.5E9
2,    out = ~out  after every (0.5e9 / (f0 + kvco * vin))
then the period of signal out is about 666ms, I think it should be 666ps. I delete 'e9' ,and I got the wrong answer.
why?

PLLTOP:  timescale:10ps / 1ps
VCO:      timescale:1ns / 1ps

in plltop:
   capacitor #(.c(30n)) C (err, err2);
   resistor #(.r(200)) R (err2, gnd);
   vco #(.f0(1.5E9), .kvco(50.0E6), .rin(100k)) VCO (.ps(err), .ns(gnd), .out(out));
in vco:
parameter real f0 = 100k;                    
parameter real kvco = 10k;                  
parameter real rin= 100k from (0:inf);

question:
1,   what does this mean?
capacitor #(.c(30n)) C (err, err2);
resistor #(.r(200)) R (err2, gnd);
2,  it is different for fo,kvco,rin in plltop and vco. why? How dose this work?

mustangyhz wrote on Nov 17^th, 2010, 6:09pm:


The first line is an instance of "capacitor" named "C", with its terminals connected to nodes "err" and "err2" and a value of 30n.
In SPICE:
C err err2 30n
Similarly, the second line would be
R err2 gnd 200

I have solved all these problems!

simulation results_2:
Dose anybody know why there is about 3 ns phase difference between fref and the feedback, the two input signal of the pfd?