what do you mean by models? for process foundry will characterize all bsim modeled parameters correspoding to every element.

Thanks.

During the R&D stage of a new process node, there will be several design of experiments around each component that will be available to the designers in the new technology. For a mos transistor, these will include variations in gate oxide thickness, channel implants, drawn sizings, spacings between junctions etc, etc.
Once the desired response surface for the transistor is agreed upon, then transistors can be made with nominal target values for all process parameters and all device specification parameters (slow, fast etc).
These are used for parameter extraction of the spice models which can mean extracting hundreds of BSIM4.X parameters for each transistor at a range of temperatures and and extremes of expected processing (3 sigma for example). The spice model is then fixed for this component and used for the PDK. The symbol for the component is also designed (for example a LDMOS device may have six or more nodes, not just gate drain source and body). The P-Cell layout is also designed and the parasitics as a function nof the layout are derived. All these go together into the PDK.
So a designer may just see a simple graphic of an nmos transistor that can be moved about the ciomputer screen with a wee mouse. But behind that simple symbol for a nmos transistor was years of man hours.