The foundry probably won't let you put the noTile mask everywhere, but I think you should try to put it over the high-frequency signal path (and possibly other sensitive areas).

Are you sure that it's a good idea to have M2 floating? I'd rather make a low-ohmic connection to a quiet ground or supply (assuming that the M3 line is differential).

When you have a floating conductor between two capacitor plates, their effective distance is essentially reduced by the thickness of the conductor, so the capacitance increases.

Matteo,

Putting fill blocking layer over your M7 signal lines is a very good idea!  You may have some troubles meeting minimum density rules though if these signal lines are big and are used over a large part of the chip.

Is M6 a thick metal in your process?  If so and you are having problems meeting density you can consider only block the thick metals underneath your wires.  It is usually no trouble meeting global density requirements on the thick metals because you are using them for power routing and such.  It may be an issue on local density depending on the window size in your process.  

I say this because the thin metals really don't make too much of a difference, particularly if you have a single-ended circuit.  I built a 6 GHz LNA about 2 years ago in 65nm CMOS and I was forced to allow fill underneath signal wires and capacitors.  What, I did was to build my own layout cell that had the minimum allowable metal density, then I tiled it under my MIMCAPS and thick metal routes.  I found that the autofill routine put down more metal than necessary and also caused a little bit of mismatch between differential capacitors.  My LNA came back from fab working great.

Good luck,
Carl