priyanka
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Posts: 4
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Hi,
There are no if-else statements. I have a basic module called "tdc" which is analog in nature. My system contains several TDCs (in the order of hundreds) and it would be tough to declare them manually. Therefore, I use 'generate' construct.
I need to process the outputs of all TDCs and my signal t_out is used for this purpose. My intention is to analyze few parameters at system level. But I am not able to instantiate the TDC block several times at the top level.
My code snippet is as follows:
wire [0:79] t_out;
generate genvar q; for(q=0; q < 10; q = q+1) begin: I_mod tdc t0 (.start(start), .stop(stop), .out(t_out[8*q : (8*q + 7) ] ) );
end endgenerate
Such a code gives the following error during elaboration: "tdc I_mod[0] has got declared analog discipline "electrical". Use of analog element inside Generate statement is not yet supported"
I hope I was able to convey my problem. Please let me know if it is possible to do it any other way!
Thank You!
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