Verilog-A and Verilog use different concepts to handling signals - Verilog-A is close to Hspice built-in model in that it uses real-valued voltage and currents that are evaluated at every time-step of the simulator. Such a signal does not know about 'Z' (or 'X', '0', or '1' for that matter) - it depends on the connections to the rest of the design and on the loading and driving impedances at these connections.

What simulation environment do you intend to use? Why is Hspice not good for determining wake-up time? Do you do RTL or transistor-level?

Cheers,
Marq

The distinction between 'Z' and '1' at transistor level can only be made in a test bench that loads the output. For instance, a small current-source load would start to pull a 'Z' state down while a '1' state stays up. By detecting the onset of the pulldown for a '1'-to-'Z' or the onset of a pullup for a 'Z'-to-'1' you can determine the wake-up time. If you do this for two or three values of the load current, you should be able to determine the wake-up time and its dependency in the load (or fan-out).

That's how I would approach the problem, at least. I think you can capture this in .measure statements without a problem.

Cheers,
Marq