Hello,
Kindly help me to get a grasp on this.
While analyzing a simple current-starved VCO structure (see pic) I noticed a behaviour, which I could not reason out why its happening that way.
My question is neither related to the simulation nor to its convergence problems. So I assume, the fact that I'm using Cadence 5.10.41 or Spectre 7.1.1 does not play a momentous role here.
It also needs to be mentioned that the VCO works as intended showing a fair tuning curve as well. However, I am more interested in knowing the response between the terminals as marked in the figure. One small note to the actual schematic is that it consists of an additional 1
Ω resistor between the Vdd supply and the output node, so that its convenient to plot the current and voltage outputs.
Question:
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On a PAC analysis, the frequency response [with the output taken at the node where 'all-pmos-bias-stages-join-their-sources' and the input applied at the 'gate-of-nmos-bias-stages'] shows a magnitude curve that falls off with a 20dB/dec slope directly from the lowest frequencies of the freq axis.
But, I expected a flat magnitude curve
along the lower frequencies of the x-axis. How can we attribute such an integrator-type response to this circuit?
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Thanks for your effort!