Hello,

Kindly help me to get a grasp on this.

While analyzing a simple current-starved VCO structure (see pic) I noticed a behaviour, which I could not reason out why its happening that way.
My question is neither related to the simulation nor to its convergence problems. So I assume, the fact that I'm using Cadence 5.10.41 or Spectre 7.1.1 does not play a momentous role here.

It also needs to be mentioned that the VCO works as intended showing a fair tuning curve as well. However, I am more interested in knowing the response between the terminals as marked in the figure. One small note to the actual schematic is that it consists of an additional 1Ω resistor between the Vdd supply and the output node, so that its convenient to plot the current and voltage outputs.



Question:
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On a PAC analysis, the frequency response [with the output taken at the node where 'all-pmos-bias-stages-join-their-sources' and the input applied at the 'gate-of-nmos-bias-stages'] shows a magnitude curve that falls off with a 20dB/dec slope directly from the lowest frequencies of the freq axis.

But, I expected a flat magnitude curve along the lower frequencies of the x-axis. How can we attribute such an integrator-type response to this circuit?
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Thanks for your effort!

Here is the Voltage Gain plot from the PAC analysis.
Also, the Transconductance plot shows a curve with a same shape.

hello all,
sorry to deviate from main topic, can any one please explain
1.Why we need to do PAC for VCO.
2. If so in vco you don't see any input so in such a case where would you apply ac source?

Thanks.

the Wavefunction,
   I cannot understand where you have placed the output of the PAC analysis, but I can say it is the nature of oscillators that they exhibit that 1/f or integrator characteristic. It stems from the fact that they are autonomous and so the phase of the oscillator is able to float. This behavior is explained starting on page 9 in http://www.designers-guide.org/Analysis/rf-sim.pdf or starting on page 26 in http://www.designers-guide.org/Theory/cyclo-preso.pdf.

-Ken

Thank you all for your considerate replies!

philcorb,
What you mentioned is correct when it comes to the working frequency of the ring oscillator.
But, isn't this frequency axis here a different one? If not, maybe I need to look into this direction.

raja.cedt,
The key to both of your doubts is detailed in the standard Spectre RF Manual.
To keep it short, an oscillator has a time-varying operating point.

rfcooltools.com,
Sorry for the confusion created. This figure is just the oscillator part of my whole schematic.
I have omitted here the biasing stage - an nmos with a pmos diode-connected load. Net11 is thus joined to the pmos gate.

Ken,
I have taken the node current at the top most node where all the pmos emitters join, as the output.
I shall look into these references to grasp this point clearly. Thanks.

loose-electron,
We take the outputs of all 5 stages together to the next circuit stage.
I shall go through the paper on differential architecture as well. Thanks for the suggestion.

Cheers!