I want to simulate a fractional-N PLL. So, I designed a 1st order sigma delta modultor to contol a 2/3 divider. I simulate this modulator in IUS. it works! But, I failed when I simulated it with AMS after making it a cellview.

code:
`timescale 10ps / 1ps

module sdm1(clk, rst, v_out);
input clk, rst;
//input [28:0] k_in;
output  v_out;
reg  v_out;
reg [28:0] a1;
wire [28:0] s1,q1;
wire  c1;
//assign s1 = 29'b00100110011010011010110101000 + a1;
assign s1 = a1;
assign c1 = {s1[28]};
assign q1={s1[27:0] };
always@(posedge clk or posedge rst)
begin
     if(rst) a1<=29'h0;
     else a1<=q1;
end
always@(posedge clk or posedge rst)
begin
     if(rst)
     begin
           v_out<=1'b01;
     end
else
     begin
           v_out<=c1;
     end
end
endmodule

why?
anybody can help me?

The test file in ius:
`timescale 1ns / 1ps

module test;

reg clk;

reg rst;

//reg [28:0] k_dth;

reg [31:0] bout_sum, clk_sum, averange;


wire bout;



modulator M1(clk, rst, bout);



always #42 clk = ~clk;



initial

begin

   bout_sum = 32'b0;

   clk_sum = 32'b0;

   averange = 32'b0;

   clk = 1'b0;

  // k_dth = 29'b0;

   rst = 1'b1;

 //  #98 k_dth = 29'b00100110011010011010110101000;
//4cd35a8

   #0.01 rst=1'b0;

   #100000 $stop;

end



always@(posedge clk or posedge rst)

begin

if (rst)

 begin

 bout_sum = 32'b0;

 clk_sum = 32'b0;

 averange = 32'b0;

 end

else

 begin  
           bout_sum = bout_sum + bout ;  
           clk_sum = clk_sum + 1;  
           averange = {bout_sum,28'b0}/clk_sum;
     
 end

end

endmodule

I have solved the problem
ConnRules
/usr/ius/tools/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_full_fast/co
nnect
Vsupply=1.8V