Jacki
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Also, if the ripple is large, and the clock frequency is closed to the signal frequency, I am afraid of the power noise which could reduce the SNR a lot. The high voltage circuit has the re-generative block at the load. So I don't think the PSRR+ can be good for the high voltage circiut. I just wonder if there is a stable power boost conveter? By the way, Fully integration is preferred, and inductor should not be used in the design since it is huge in the layout while not every CMOS technology has the inductor cell in their library. Any comments? Thank you Jacki
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