hi every one,
i am designing differential Charge pump based PLL. Please find the attached CP schematic. i am expecting Vref will impact charge pump mismatch but my common mode reference is varying +/_ 20mv across corners and this leads to 12% mismatch. Can any one please tell me is there any Diff charge pump  architecture which can have less impact ?

Thanks.

hi,
if vref go down,common @ charge pump has to go down and so as to happen this down current has to go high. My common mode varies by around 20mv across corners.
By the way mismatch i am talking is not random mismatch.

Thanks.

Hi Raja!

Have you checked that your current source transistors are into saturation, Vgs>Vgs,sat?

Your CM loop is comparing the lowest voltage of the Vctlp and Vctln to Vref and then feedback the result. This will work if Vctlp and Vctln are swingning around the same CM voltage, if you have some LP filtering somewhere. But your PLL-CP will have a DC voltage between Vctlp and Vctln when the PLL is locking the VCO to the correct frequency. Then your CM loop will put the lowest of Vctlp and Vctln equal to Vref. The highest of Vctlp and Vctln will be much higher, and maybe put the PMOS current sources into the linear region.

The trick with the three transitor diffstage to the left will work in a opamp with swing but I do not think it will work here. I suggest you sense the Vctlp and Vctln voltage with two source followers and connect the sources together with two resistors and use the middle point together with Vref to get the error signal for the CM loop.