Hello everyone from a new member,
Congrats for this amazing effort!!

I am currently designing a bandgap reference (BGR) circuit in IBM cms9flp.

Using Assura for LVS the circuit is shown to be correct (layout schematic match, and no extraction problems)

When I use Calibre the result is Correct again, there are no extraction problems, BUT there is an ERC error. The description of the error is:
ERC2
All NWELL Regions should be tied to POWER or most positive chip supply. FRom LVS deck, NWELL = NW NOT (N3 OR NWRES OR NW_RES)

but it points to my vertical pnps (I have taken care to properly bias the nwell all the PMOS in the circuit)

The base of the vpnp pcell is connected to the nwell. But in BGR circuits the collector and the base are both connected to ground. So, this nwell is connected to ground, and not to a POWER net, and thus, I get the ERC error.

But I believe there would be no problem in practice, since the collector (that is the substrate) and the base (that is the nwell) are both connected to ground, and thus the parasitic substrate-nwell diode will never get forward biased and conduct current.

According to this rule, I would get no error only if I connected the base of the vpnp to a POWER net eg VDD, but then the vpnp would be a useless device!! (because Veb would be zero or negative)

I think that there should be an exception in this rule, when the nwell belongs to a vpnp.

Has anybody faced this problem again?
I would appreciate if you shared your view on this issue.

Thank you very much in advance,
mix