rfidea wrote on Jan 27th, 2011, 1:31am:Since your PLL is multiplying the frequency of the reference with 400M/20M=20 the reference must be much better than 1/20 of the PLL spec, which is 2deg/20=0.1deg.
To me, it seems not correct. Assuming the PLL is ideal frequency multiplier, output_frequency=input_frequency*N. If we allow a 2 degree jitter on the output frequency, the input frequency jitter should also be 2 degree. Example is: output frequency period=10ną1n, then input frequency period should be: N*(10ną1n),
in terms of degree, it is the same.