Hello evryone,

I have two queries which I am listing below:

1.
I am trying to model a verilog A model of continuous time bi directional shift registers.
Based on the input signal and clock the output can be either incremented or decremented by one (normal bi directional shift register operation).

I have clock and input signal as my input and N (variable = 8 to 512) output ports. All in continuous time. There is no sampling done anywhere. The clock mentioned above and in the code is another signal which is being used as clock to perform the operation (kind of asynchronous operations).

Code I have written is as shown below:



@ (initial_step)begin
for (i=0; i<256;i=i+1)
   begin
     result[i]=0;    // temp location to store result initialize to zero
   end

end // initial

@(cross(V(clk)-clkThresh, -1)) begin
 sampleIn = V(vIn);                             // vIn is the input voltage
  for (i =0; i<N; i = i+1)
      begin
     if (sampleIn >=0.5)
        begin
            result[0] = 0;                   // first bit set to zero
                result[i+1] = result[i];       // rest all shifted right
        end
     else if (sampleIn < 0.5)
        begin
          result[i] = result[i+1];       // all bits shifted to left
          result[N-1] = 0;               // last one set to zero
        end
     end    


// final assignment of the output signal

for (i =0; i<N; i = i+1)
V(srOut[i]) <+ transition(result[i], td, tr, tf);

end module


My problem is I am not able to model the N output ports in verilogA. Final assignment as highlighted in red is throwing parsing error.

'the index used to bits of analog signal vector srOut is constant, constant expression, genvar-constant expression. To avoid this problem, ensure that the index used to access the bits of analog signal is constant, constant expression, genvar-constant expression.'

Can someone please help me to resolve my problem.
Also I ll be glad to provide any information or to clarify any point if not clear above.

2.
In the variable ADC code at http://www.designers-guide.org/VerilogAMS/functional-blocks/data-converter/conve...
can some one please explain me the ussage of following statement:

localparam integer levels = 1<<`bits;


Thanks
xyzLinkoping

A bit of explanation: the genvar is needed because this is an analog for-loop. The transition filter inside your for-loop body must be evaluated at every time step exactly the same number of times. The use of a genvar as index variable forces that behavior as the only locations where you can assign a value to a genvar are the index initialization and index update parts of a for-loop:

for (<index initialization>; <index condition>; <index update>)
 <statement>


Cheers,
Marq

Hi DC,

yes, everything in Verilog-A is also valid in Verilog-AMS. Verilog-A is a defined subset of Verilog-AMS - defined in Annex C of the Verilog-AMS standard.

Cheers,
Marq

Hi Marq,
Thanks for your reply and suggestion on test bench.

BTW the code is working but not giving the correct output
I need to check the logic now... it may not be correct for bidirectional shift register.

Rgds
DC

Thanks Geoffrey_Coram for pointing out the problem in the code.

Can someone help me with some handy snippet of Shift Register modelling in verilog (or infact in any other HDL). It will be really nice.
(Or may be a bit modification in my earlier code which I believe should work with some modification)

Thanks
DC

Thanks Geoffrey_Coram,

I will test it today in my test bench.

Best Rgds
DC