I know the equation, but also want to give a simulation plot of SNR (Noise from sampling jitter) for an ADC. I tried to search websites but cannot find the answer.
The key problem is how to generate a clock with controllable jitter, which cannot be found that in simulink help. Thanks a lot!

I saw the same post in edaboard.

There is another thread on that very board that you can refer to
http://www.edaboard.com/thread57284.html