Why don`t you post a circuit diagram? Otherwise it is not easy to answer your - more or less general - question.

Rakesh,

Loop gain is defined with regard to a small signal linearized equivalent circuit.  The values of the components in the small signal equivalent circuit are established by the DC operating point of each component in the original circuit.   The transistors in the original circuit have small signal equivalent models whether they are operated in the linear  region, or the active region or the substreshold region, etc.

Therefore, to calculate the loop gain at a particular DC operating point,  I would first determine the small signal equivalent circuit of the original circuit at that operating point.  Then analyze the loopgain using the small signal equivalent circuit.

Garrett Neaves

I too agree with garrett. In this case of back to back inverter. what is the operating point as signal will swing all the way to rail as its a positive feedback system. Where to linearize the system to calculate the gm of the transistors.

If we calculate using small signal model we get the loop gain to be very small  at the beginning since the transistors are in linear region.

Loop gain will only be high if we linearize the circuit when both the transistors are in saturation regions.

So if we have any noise in the circuit (around Vdd) at one input  if we see via loop gain we dont get any modification of noise  due to lower loop gain...

However we know noise rather dies out ..
Is is possible to explain in terms of loop gain here.
Is it that due to noise having path to ground or vdd is removed with time.

Rakesh,

  You are looking at the problem backwards. The latch does not go
out of latch unless forced, for example, by shorting a switch across
the inverters. You solve the problem by assuming that the two inverters
are biased at their switching threshold, i.e., the level of the input and
output the instant after that ever so helpful switch opens. In this case
all the transistors are biased in saturation, both the inverters have
gain, and the loop gain is large, >>1.

                                                                  Best Regards,

                                                                     Sheldon

By the "latched state", I mean that state in which neither gate is being externally forced.