Marq Kole
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Hmmm. That's weird...
Posts: 122
Eindhoven, The Netherlands
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Hi,
If you recode it in integer arithmetic it should work fine. working with regs works only well from the digital side. Assignment to regs (procedural assignment) should be done in an always block, not in an analog block. Always blocks are not supported in Verilog-A. Field widths do not have a meaning in Verilog-A as everything is mapped onto integers that have a fixed width of 32 bits.
Your code indeed can be readily used in a Verilog-A analog block. You can leave out the field widths for the literals as they're not honored anyway.
Cheers, Marq
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