wave wrote on Mar 7th, 2011, 11:11am:Steve - Read up on Latches and Flip Flops.
In b), consider the feedback inverter weaker than the fwd path.
~Wave
Hi Wave,
u r right, (a) is d latch, by defintion it outputs signal when clk comes (here switch S1) and maintain the signal otherwise, so is what i said correct or I'm still missing the point, please clarify. and btw, what's the difference between this d latch and the more general one that uses two NAND (or XOR) ?
for (b) can you elaborate? i'm a little bit slow
thanks,
Steve