Hi,

While stabalizing continuous time CMFB of a two stage miller compensated amplifier, I am saw some funny results with the CMFB's AC response. These results are attached as a pdf with this post. For the simplicity, I made a single ended  input output amplifier replicating the same CMFB path and reproduced the same results.

I am using 130nm digital transistors from a reputed foundry. The observations are made by chaging the size of the PMOS tail current source alone. During these obeservations, all trasistors are in saturation with sufficient margins. Test bench to test the AC response is also mentioend in the attachment. For all the tests, load capacitance is 400f.

There are the observations:

1. There is a peaking in the gain responce at around 10MHz which does not come in my calculations at all.
2. When W/L of tail transistor is changed from 2u/1u to 3u/1u, there is a considerable change in the phase response which I don't expect to happen.
3. When I replace EITHER the first or second stage's PMOS tail transistor with the ideal current source and equivalent parasitics, I get the correct response.

I don't understand why AC respnse behave normally with either of the PMOS tails is replace with ideal current sources. I also don't understand the peaking and sudden phase shift.

Please shed some light on these results, tell me if there is some issue with my testbench, my understanding or my process.

Regards, Tron

I have pretty much the same doubt as aaron_do. As far as I can see it is the only loop present in your amplifier. So how do you bias your upper p-mos transistors? You could check whether some capacitance on that node kills this peaking.