Hi, all,

I am drawing the layout of my RF CMOS circuit, but it can not pass the LVS due to the LVS_RF layer(it is only for LVS, as the Design Rule said). If I delete this LVS_RF layer and change the RF MOS to analog MOS in schematic, it can pass the LVS.

So the problem is that, are the RF MOS and analog MOS the same in fabrication(such as doping etc.), and the different is only the model in simulation?

Regards,
Christon

Usually the RF MOS is fixed size transistor with fixed metal connections. Those connections are added to the model as an external network. But the basic transistor is the same.

I guess the LVS_RF layer is informing the LVS tool that this is a RF MOS and not an Analog MOS. Have you done something extra to the layout, such as connecting is some other layer compared to the one in the fixed layout? This could be the reason for LVS fail.