Hello,

I'm using verilog models of a dual port ram memory.
When operations are done simultaneously at the same address on the two ports without respecting the Tcc timing constraint a collision occurs, WriteA/ReadB for example. In this case the Read on the port B fails and the output is corrupted (put at X). In order to check the Tcc timing constraint the task $recovery is used:
$recovery(posedge CLKA &&& csba_en,posedge CLKB &&& (flag_collisionB ==1'b1), tcc, warningCCB);
Using this task makes it possible to back annotate the tcc timing constraint (with SDF file) and to check collision violations.

Unfortunately the $recovery task generates an error message in the log when the collision occurs.
I do not want to have these error message, so I was wondering if it is possible to skip this error messages, or to modify this system task in order to delete the error message. Any idea ?
Thank you

Thank you for your response.
I write the models and It will be used by other persons, so setting the simulator may not be an optimal solution.

Is it possible to get the code of this system task in order to rewrite it ?

My aim is just to be able to back-annotate the tcc timing and check collisions whitout generating error/warning messages

I certainly remember that for ncverilog and vcs simulators there was some input option which suppress he messages. Unfortunately don't remember the name.

Regarding to PLI,not sure that you will fins a solution because displaying warnings is simulator option.