lhlbluesky_lhl
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in switched capacitor circuits (such as sample-hold circuit), the input signal is sampled at the falling edge of the sampling clock, i want to know, what is the exact sample instant in the following sampling clock? A, B, C or D? in real case, the voltage at the four nodes may be very different (the difference of output voltage can be 2mV or so, especially for small input signal), so, what is the exact sample instant, and when should i sample the input signal at the falling edge of the sampling clock?
please help me, i'm confused about this, thanks all.
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