in switched capacitor circuits (such as sample-hold circuit), the input signal is sampled at the falling edge of the sampling clock, i want to know, what is the exact sample instant in the following sampling clock? A, B, C or D? in real case, the voltage at the four nodes may be very different (the difference of output voltage can be 2mV or so, especially for small input signal), so, what is the exact sample instant, and when should i sample the input signal at the falling edge of the sampling clock?

please help me, i'm confused about this, thanks all.

i use cmos switch here, and any other ideas?

Of the 4 points marked, it is closer to 0.5*(VH-VL). If you have an nMOS transistor with both its drain and source at a voltage Vx, the switch turns off when the gate falls below Vx+VT. (As others pointed out, this is not instantaneous and there will be some averaging over a certain aperture, but works for a first order).

To make the sampling instant independent of the input signal, use bottom plate sampling for example. Here the sampling instant is determined by a switch whose ends are at a given bias voltage with no signal component.

A search for "bottom plate sampling" on the web will give you the topologies.

BTW, the spectrum of the sampled signal will be sensitive to the sampling phase as long as the sampling is periodic, although the samples themselves are different depending on the phase of sampling.

Nagendra