I tried out layout (for UMC180nm) in cadence but unable to solve some errors while generating LEF file. DRC,LVS, Parasitic extraction these are all passed. Even i am able to generate .gds file. Then i went for LEF from abstract but getting error which i attached to this topic.
              I did layout for simple inverter then i am generating layout by using "Gen from Source" in layout XL.After everything (DRC,LVS,extraction, post layout simulation) been done, i selected abstract editor tool -> create abstract- finally it is generating error. I tried to solve by dumping technology file (technology.tf, by using TECHNOLOGY FILE MANAGER) into current working directory but by this also i got the same error. I am not understanding whether the problem is with the technology file which is given from foundry or some thing else. If any one could reply me it would be really helpful.