Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Aug 16
th
, 2024, 9:30pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Design Languages
›
Verilog-AMS
› induced gate noise of a fet transistor
‹
Previous topic
|
Next topic
›
Pages: 1
induced gate noise of a fet transistor (Read 3786 times)
Kem
New Member
Offline
Posts: 9
induced gate noise of a fet transistor
May 16
th
, 2011, 9:36am
Hello,
I'm new here and have no experience with verilog a before. I 'm working on a FET transistor model and i have to implement it with verilog a.
I have to verify the pucel noise formula for a fet transistor.
<i_g^2>=4*R*K*T0*B*(w*Cgs)^2 / gm
The question is how can i implement <i_g^2> in veriloga ? It is more about the frequency w.
thanks a lot for your help
kem
Back to top
IP Logged
Geoffrey_Coram
Senior Fellow
Offline
Posts: 1999
Massachusetts, USA
Re: induced gate noise of a fet transistor
Reply #1 -
May 17
th
, 2011, 12:53pm
I believe both the MOS11 model (posted here) and the PSP model (pspmodel.asu.edu) contain Verilog-A implementations of correlated gate noise.
Back to top
If at first you do succeed, STOP, raise your standards, and stop wasting your time.
IP Logged
Kem
New Member
Offline
Posts: 9
Re: induced gate noise of a fet transistor
Reply #2 -
May 18
th
, 2011, 11:44pm
Thanks for pointing out the link. I have read it but i couldn't really understand it since there are comment missing.
kem
Back to top
IP Logged
Geoffrey_Coram
Senior Fellow
Offline
Posts: 1999
Massachusetts, USA
Re: induced gate noise of a fet transistor
Reply #3 -
May 19
th
, 2011, 10:24am
A better introduction is
C. McAndrew, G. Coram, W. Grabinski, A. Blaum, and O. Pilloud,
“Correlated noise modeling and simulation,” in Proc. Workshop on Compact Modeling, 2005.
I think you can get the slides here:
www.nsti.org/Nanotech2005/WCM2005/WCM2005-CMcAndrew.ppt
The paper is here:
www.nsti.org/procs/Nanotech2005WCM/1/T46.03
but you have to buy the proceedings.
Back to top
If at first you do succeed, STOP, raise your standards, and stop wasting your time.
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
»» Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.