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induced gate noise of a fet transistor (Read 3755 times)
Kem
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Posts: 9
induced gate noise of a fet transistor
May 16
th
, 2011, 9:36am
Hello,
I'm new here and have no experience with verilog a before. I 'm working on a FET transistor model and i have to implement it with verilog a.
I have to verify the pucel noise formula for a fet transistor.
<i_g^2>=4*R*K*T0*B*(w*Cgs)^2 / gm
The question is how can i implement <i_g^2> in veriloga ? It is more about the frequency w.
thanks a lot for your help
kem
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Geoffrey_Coram
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Posts: 1999
Massachusetts, USA
Re: induced gate noise of a fet transistor
Reply #1 -
May 17
th
, 2011, 12:53pm
I believe both the MOS11 model (posted here) and the PSP model (pspmodel.asu.edu) contain Verilog-A implementations of correlated gate noise.
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Kem
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Re: induced gate noise of a fet transistor
Reply #2 -
May 18
th
, 2011, 11:44pm
Thanks for pointing out the link. I have read it but i couldn't really understand it since there are comment missing.
kem
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Geoffrey_Coram
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Posts: 1999
Massachusetts, USA
Re: induced gate noise of a fet transistor
Reply #3 -
May 19
th
, 2011, 10:24am
A better introduction is
C. McAndrew, G. Coram, W. Grabinski, A. Blaum, and O. Pilloud,
“Correlated noise modeling and simulation,” in Proc. Workshop on Compact Modeling, 2005.
I think you can get the slides here:
www.nsti.org/Nanotech2005/WCM2005/WCM2005-CMcAndrew.ppt
The paper is here:
www.nsti.org/procs/Nanotech2005WCM/1/T46.03
but you have to buy the proceedings.
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