Hi All,

         I am trying to implement a verilogA model for a PLL, and am facing some trouble with the VCO part. The control voltage feeding the VCO is converted into a current. There is a well defined relationship between the current and the period or frequency. I feed this calculated period to the @(timer) statement. Here's my code for the VCO;
Code:

// VerilogA for  VCO_PLL, veriloga

`include "constants.vams"
`include "disciplines.vams"

module VCO_PLL(inp,inn,ClkOut,Irampby2src1,Irampby2src2, V330,vss);

input inp,inn, V330, vss;
output ClkOut, Irampby2src1,Irampby2src2;


electrical inp,inn,ClkOut,Irampby2src1,Irampby2src2, V330, vss;


real x, ramp_curr, int_period, halframp,del,ts,t_redge,t_fedge;
integer state,state_high,state_low,temp;

analog begin

@(initial_step) begin
state=0;
temp=0;
int_period=1.0;
del=1.0;
$strobe("done");
end

x=V(inp,inn);

@(cross((x-0.6),+1)) del=$abstime;

ramp_curr=abs(1e-06*pow(x,6)-1e-05*pow(x,5)+4e-05*pow(x,4)-6e-05*pow(x,3)+4e-05*pow(x,2)-8e-06*x+2e-07); //V to I



I(Irampby2src1)<+(-0.5)*ramp_curr;

I(Irampby2src2)<+(-0.5)*ramp_curr;

halframp=I(Irampby2src2);

int_period=1/(2e11*ramp_curr); //calculate the period

ts=0.5*int_period;

@(timer(del,ts)) begin
$discontinuity(0);
state=!state;
//$strobe("edge");
end

$bound_step(0.3*int_period);

V(ClkOut)<+V(330,vss)*transition(state,10n,int_period/100);

 

The problem basically manifests itself in the following way:

the variable "state" randomly changes state even when $abstime is not a multiple of period/2. This is not something that happens every cycle, but in a 400 us simulation, it happens at a couple of random time points. Peeking at the period variable shows that it has remained unchanged, thus precluding the possibility of that causing the change in state.

Is there something about the way @(timer) works that I am not accounting for?

Thanks and Regards,
SJ