dear all,
i want to concatenate a register(of dynamic size as for concatenation)
with n no:of zeros where n is a  generic integer number.

say for eg
num1_reg := "00" & num1;--here only two zeros are only used

i would like to make it something that would work like this

num1_reg := "N zeros" & num1;--wherein n is a generic number

how to make it work..please advice...
thanks in advance

VHDL only not verilog

thanks boe.tat was of gr8 help

actually tat was not i was lookin for.the type-subtype wont help me b'coz the size of the main type cant be determined unless the n(for the zero's or for the main pgm) is assigned,moreover as you said the a large size for the vector is also not adviced i suppose!!