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PSP 101.3 Verilog-A Model Problem
Jul 08^th, 2011, 8:49am

Hi,

I am using the Verilog-A version of the PSP 101.3 model to model one depletion and enhancement type device (all nmos). I have extracted the various DC parameters, and have reasonable fits for the model.

The problem is, when I simulate a simple inverter, with a depletion device on top, and a current source at the bottom, with the gate and source of the depletion device tied together, and a 16V rail DC supply to the depletion device + current source. When I sweep the current source from 0 to 20 fA (femto), I see that the output voltage (the source/gate terminal of the depletion device, which are tied) to start at 23V! constant for a few fA and then ramp down to below 16V. This is bizarre behavior, where the MOSFET has approximately -5V across its Drain-source, but a positive current flowing from the drain to the source.

Does anyone know what this problem might be?

Any information regarding this would be very helpful.

Thank you,

Mihir

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: PSP 101.3 Verilog-A Model Problem Reply #1 - Jul 8^th, 2011, 10:28am Check the GMIN term; there was a bug in some versions of PSP where I(D, S) <+ Vds * `GMIN; and Vds would be swapped (Vds = - V(D,S) so that Vds >=0 always). Is it an ideal current source? I'm having trouble visualizing your circuit; it would help if you provided a schematic.
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Mihir Mudholkar

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Re: PSP 101.3 Verilog-A Model Problem
Reply #2 - Jul 8^th, 2011, 12:45pm

Hello Geoffrey,

Thank you for your input. I have attached a schematic of an inverter that I am simulating with a depletion device on top and enhancement device at the bottom.

I have identified the problem to be with the depletion device on top, because when I replace the top device with a 10k resistor, the simulation shows correct output.

I have tested the depletion device model using the following tests
Sweep1: VGS = 0 (Gate connected to Source), VDS Swept from 0 to 15V, measure ID (~3.3mA at VDS = 15V measured)
Sweep2: VGS = 0 (Gate connected to Source), ID swept from 0 to 4mA, measure VDS (~15V at 3.3mA)

So the model is behaving correctly in both scenarios, when we sweep either VDS or ID.

However, in the transient simulation, it can be seen that when the enhancement devices are turned OFF (middle graph is the gate-signal to the bottom enhancement device), the depletion device is not pulling the output all the way back to ~ 16V which is the DC bus voltage.

Peculiar.

Mihir

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inverter_test_ckt.png

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Mihir Mudholkar

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Re: PSP 101.3 Verilog-A Model Problem
Reply #3 - Jul 8^th, 2011, 12:48pm

Also attached is the output waveform
Top graph is the current through the depletion device
Middle graph is voltage applied to the bottom enhancement device
Output voltage is the bottom graph.

In my original question, the enhancement device at the bottom was replaced with an ideal current source, and it was swept from 0 to 20fA yielding the output voltage at 23V in the beginning

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inverter_test_waveform.png

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: PSP 101.3 Verilog-A Model Problem Reply #4 - Jul 12^th, 2011, 10:28am Quote: an ideal current source, and it was swept from 0 to 20fA 20fA isn't much current; through a 10k Ohm resistor you won't get much voltage -- probably not enough to notice on top of the 16V rail. Are you sure the ideal current source had the right polarity?
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Geoffrey_Coram

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Re: PSP 101.3 Verilog-A Model Problem
Reply #5 - Jul 12^th, 2011, 10:33am

Mihir Mudholkar wrote on Jul 8^th, 2011, 8:49am:

When I sweep the current source from 0 to 20 fA (femto), I see that the output voltage (the source/gate terminal of the depletion device, which are tied) to start at 23V! constant for a few fA and then ramp down to below 16V.

When I read this, it sounds like the time=0 value of the current source is 0fA, and the output voltage is 23V. Do you have some .ic statement? Where does that 23V come from? (An ideal current source can force a voltage above the voltage source values, but not when it's sourcing 0A.)

If you do a dc sweep of the source current, do the values make sense?

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