SARAM wrote on Aug 10th, 2011, 8:00am:I think I used default connect rules.
Type: built_in
Rules Name: ConnetRules_18V_full_fast
how can i change this value?
Read the (AMS designer) documentation.
Quote:one more thing, the file is sampled equi distances but when i see the figure and show the the points i see variable sampling that somehow it is not related to my input file. why is that?
Check the output of your vpwlf source and compare with the input of wrealdff. You will see that the interface element between the "analog world" (signal discipline electrical at vpwlf) and the "digital world" (wreal) transfers changes only from the analog to the digital domain if the analog input has changed by more than some mV. Otherwise the simulation of the digital part would be slowed down.
For more details refer to Verilog-AMS LRM on absdelta events.
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