hello all,
Can any one please tell me is this circuit have -ve feedback around the opamp? i feel gain from the M1,M2 stack will be more than M3,M4 stack, so in this case +ve feedback is more dominant than -ve FB.

Thanks.

This particular circuit looks odd, but I've seen similar discussions on Bias circuits.  (either a delta VBE bipolar loop, or delta Vgs MOS loop).

Often a amplifier is used to control the PMOS current mirrors.
(as drawn, I'm not sure the Amp is controlling the circuit much on the Nmos cascodes).
Basically M3 is lower impedance than the M2 side.
This will influence the gain, and the "polarity" of the op-amp hook up.
It's not the most direct circuit to analyze, so I'm assuming/guessing that the question --- is it Positive or Neg. Feedback?

Raj - make sense?


~Wave

hello guys,
ya you are correct for this kind of circuit it's hard to say which one is +ve and which one is -ve. But so as to make operating point stable we ned to ensure if any distrubance occur any where finally loop should restore previous operating point. In that sence i applied some signal at the o/p but it's keep on diverging rather converge.

other wise...for get about all the discussion above and just tell me wether opamps polarity is correct or not.
Thanks.

hello buddy poor,
nothing is there, shown is the total circuit.

hello buddypoor,
please find the attached fig. So correct me if am wrong any where.

Thanks.

raja.cedt,

There is no (significant) feedback around the opamp. Break the loop at the opamp output, inject a test signal to the gates of M1,4, and see what returns at the opamp output. Assuming transistors with gds=0 and current sources with a finite Rout, the test signal at the gates of M1,4 creates a current of 2/gm*Vtest in M4,3 which is also mirrored to M2. M1 acts as a cascode. So the difference voltage across the opamp inputs is zero. A non-zero gds modifies this calculation only slightly. Bottomline, don't use this circuit.

Hi,
 Assume that M4, M1 gds to be zero and M2 and M3 has finite gds.
Break the loop at gate of M4 and M1.
the current produced in transistors will be (gm/2)Vtest+(gds/2)Vtest on the left side and (gm/2)Vtest + gm/(1+gm/gds)Vtest on the right side.
Both sides transistors M1 and M4 acts like a cascode transistor with degeneracy 1/gm and 1/gds.
Now (gm/2)Vtest is common to both sides.

Since we have at the top ideal current sources
the extra current should flow into the out put impedances at the drains of M4 and M1.
The voltage developed at the +ve terminal of opamp will be
(1/gds) (gm/2 +gds/2)Vtest.
The voltage developed on the negative terminal will be
(gm/2 + gm/(1+gm/gds))(gm/gds^2)Vtest
The difference at the input of the opamp is approximately
gm/2(1/gds -gm/gds^2)Vtest + (0.5-gm/gds)Vtest
Assuming gm/gds >>>1
we have
difference as
-gm/2(gm/gds^2)Vtest-(gm/gds)Vtest
if the gain of the opamp id A
then at the output of opamp we have a loop gain whcih is negative  and high due to negative feedback as
-gm/2(gm/gds^2)A-(gm/gds)A

So i think the signs on the opamp is correct

Correct me if i am wrong
Thanks

hello nrk1,
thanks for your note. ya i forgot this. But from erlier post gain from gate of m1 is zero but one thing is m2 gate also moves due to m4,m3, correct me if am wrong.

Thanks.