This particular circuit looks odd, but I've seen similar discussions on Bias circuits. (either a delta VBE bipolar loop, or delta Vgs MOS loop).
Often a amplifier is used to control the PMOS current mirrors.
(as drawn, I'm not sure the Amp is controlling the circuit much on the Nmos cascodes).
Basically M3 is lower impedance than the M2 side.
This will influence the gain, and the "polarity" of the op-amp hook up.
It's not the most direct circuit to analyze, so I'm assuming/guessing that the question --- is it Positive or Neg. Feedback?
Raj - make sense?
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~Wave