I write a simple DLL circuit using verilogA.
I use a transition function to implement delay function in the VCDL delay cells as below:

Code:

`include "constants.vams"
`include "disciplines.vams"

module delay_var(din,dout, vctrl);

	  parameter real tr=0 from [0:inf);
	  parameter real tt=1p from [0:inf);
	  parameter integer dir=0 from [-1:+1];
	  parameter real vcc=1 from (0:inf);
	  parameter real threshold=0.5 from [0:inf);

	  parameter real vctrl_min=0 from [0:inf);
	  parameter real vctrl_max=vcc from (0:inf);
	  parameter real td_min=20p from [0:inf);
	  parameter real td_max=80p from (td_min:inf);



	  output  dout;
	  input   din, vctrl;
	  voltage din, dout, vctrl;

	  integer  state;
	  real     td, td2;


	  analog begin

		    td = (V(vctrl)-vctrl_min)*(td_max - td_min) / (vctrl_max - vctrl_min) + td_min;

		    //bound the delay
		    if( td > td_max)
				td = td_max ;
		    if( td < td_min)
				td = td_min ;

		    @(cross(V(din) - threshold, dir, tt))
		    state = (V(din)-threshold>=0);

		    V(dout) <+ vcc*transition(state ? 1: 0,td,tr,tr,tt);
	  end
endmodule
 

The DLL is able to lock to the rising edge but the duty-cycle is distorted by rise_time/2 (in this case is 10ps/2=5ps), shown in the diagram  
The frequency of the output (clkout) is remained to same but with minor duty-cycle distortion.
How could I solve this?

ps: i have put small tolerance to 0.5ps

i expect the DLL will lock to the clkref without duty-cycle distortion. I do not know why it exhibits different delay between tr-tr & tf-tf since the vctrl is constant. in short, i am not sure what went wrong.

for application wise, it is just a basic DLL to alight the clock out to clkref, similar to PLL but it does not change frequency.

sorry about that. I thought it is a standard DLL schematic which the signal names will be self-explanatory
i upload the verilogA schematic. The PFD-CP is modified from the designer-guide webpage.



the PFD connection is inverted due to delay cell characterisitic is inverted

I am not intimately familiar with DLL's, but I know Verilog-AMS pretty well. If you require that someone must know what you know, you greatly restrict the number of people who can answer your question. And by restricting the information you give, you may be concealing the error. You are not alone. Few people give enough information when they ask a question.

You still did not clarify what you meant by 'duty-cycle distortion'. Is the problem that the delay on the rising edge is different that the delay on the falling edge? If so, could you regenerate the plots, this time showing the value of the module's state variable along with the other signals. We need to know if the rise and fall time differ, or whether state is staying high longer than expected.

Could you also show the parameters used on the delay cells.

Also, why do you use the dir parameter in the cross function. Would you expect the model to work if dir was set to something other than 0?

-Ken

I am not implying that you intended to conceal information. Rather, I am saying that you neglected to give information that would be needed by others that are trying to help you by answering your question. I mention it because it is very common. Often when people ask questions they only provide the information they think they would need to answer the question. I am trying to encourage people to instead think about what would be needed by people with different types of expertise. I even gave an example. I know Verilog-A well but DLLs not so well. The fact that you did not describe the the overall structure of the DLL made it difficult for me to help you.

I am sorry if it feels like I am picking on you. That is not my intent. I am just trying to get people to be a little better about the way they ask their questions so that:
1. it is easier for people to answer the questions, and
2. the questions get answered more quickly.

Could you show a plot of the value of the module's state variable. We need to know if the rise and fall time differ, or whether state is staying high longer than expected.

-Ken

You cannot plot a state variable from the schematic, instead you have to bring up the signal browser.

-Ken