Hi all,

I want to write code for simulating interpolator.
I have two clock domain  CLK_low , CLK_high.
I want to increase sample rate by this ratio CLk_h/CLK_l.

I write code below and feed it with ramp but in some place it did not work correctly.

please help

Clk_h=150 MHz;
CLK_l=61.44 MHz;

this program use linear interpolation y=(1-n)*Xn-1+n*Xn
that n is 0<n<1;

module SRC (in,out,CLK_l,CLK_h);
     
parameter integer OSR_1 = floor((1/(150/61.44))*pow(2,9));

     parameter integer scale = pow(2,9);
     

     input  in,CLK_l,CLK_h;
     output out;
     wreal  in,out;
           
     integer   fraq_cnt = 0;
     real   xn,xn_1,y_lin,frq,frq1;
     
     always @(posedge CLK_h )      begin
                 
                 fraq_cnt = fraq_cnt + OSR_1;
                 frq1     = (fraq_cnt % scale);
                 frq      = frq1/scale;
                 y_lin    =  (1-(frq)) * xn_1 + (frq) * xn;
                 
     end            
                 
     always @(posedge CLK_l ) begin
                             
                 xn_1   = xn;
                 xn     = in;
     end

                                   
     
assign      out = y_lin;

endmodule

Hi,

The previous code was written for linear interpolation.
This one was written for Zero order hold. and the same clock frequency as above.

input  in,CLK_l,CLK_h;
    output out;
    wreal  in,out;

    real   xn,xn_1,y_zoh;
   
    always @(posedge CLK_h )      begin
               y_zoh = xn_1;
               
    end            
               
    always @(posedge CLK_l ) begin
                           
                xn_1   = xn;
                xn     = in;
    end


How can I make sure that in every rising edge of higher clk system take data and do the ZOH operation?
I dont see that there are some point at rising edge of Clk_h. and also the input is a linear ramp but the output is not.

Would you please help me

Amir

Thanks B O E

Attached, you can see what you asked.
I just increase the CLK_h by factor of 2 in this figure.

if this is display problem how can i make sure the number of samples at the output were increased? I can not see the symbol in between of two low rate clk that sampled with high rate.


Regards

Hi BOE,

You mean that by this way I increased data samples at the output in ZOH manner.

another question is that how can i solve the problem with linear interpolation. (first code i have written at my first post). what can i do when two clock are async.

how can i implement linear interpolation? is there another way to implement with two async clock?

Regards,