IMO everyone needs to back up a bit and look for clues in the silicon and then verify with simulations instead of vice versa. I'm suspecting the output stage has more current than planned - this topology can have that problem. It could be from mismatch in the M19, M23, M24 and M26 loop (or the PMOS equivalent), or lower output impedance than anticipated in the output devices.
You should be able to do some tests to determine if that is the case. First, get it in a condition where it isn't oscillating. Hopefully this will happen if you move the common mode input out of center.
1) Check Idd vs Iload. If it is the output stage it should match the simulation when your load debiases the output device that isn't providing current. From this you should be able to determine if it is the output stage.
2) Is the Idd condition sensitive to power supply or the opamp output voltage?
3) Is Idd sensitive to the common mode value of the input?
The second thing I would suspect is your bias circuit. How are you biasing the amp? Beta multipliers can be very sensitive to mismatch.
4) How is the bandwidth? If it is too high then your input stage bias current might be too much.
As far as oscillation is concerned, (I think you want to figure out the Idd first), we need more info. Does the Idd error go away when it isn't oscillating? Is the bandwidth what you expect? What is the frequency of oscillation? Does it change with load current? What are your feedback and capacitive load conditions? Are the pins bonded out? Are you including parasitic caps in your simulation (especially at the inverting node and a distributed cap along the length of the feedback resistor)? How about the bottom plate of your compensation cap? How about the capacitance of the scope probe? (You wouldn't be the first.) But before you start playing with the oscillation problem spend some time with the Idd problem.
Changing temperature can also provide clues. Does putting freeze spray on it solve the problem?
In other words, start monkeying with the silicon and note the funnies. Write down the funnies and the magnitude of the funny
![Wink Wink](https://designers-guide.org/forum/Templates/Forum/default/wink.gif)
. If you can see two or three unusual sensitivities of the problem (i.e. power supply sensitivity) you can usually piece together the problem and
verify with simulations. You have the real thing in front of you so you shouldn't be searching for the clues in the simulations - use the real thing. JMO anyway.
Best,
Rob