Hello everyone.
The following figure shows the Huijsing rail-to-rail input and output opamp.
The simulation shows 3mA current consumption, but when measurement, it has two problems: (1) it shows 7mA current consumption, much higher than simulation result. (2) it shows oscillation behavior at no load condition.

Do any of you have experience about this? What may be the reson of the fail operation? Thank you so much.

Hi Wave, thank you very much for your reply.

(1) Did you get the Biases correct?  Vgs, vdsat  
Could u please explain more clearly about this?  When design the circuit, Vgs and Vdsat are checked and right to make sure the saturation operation.
 
(2) What is the sim of Loopgain look like?
Open loop gain is 130dB, Band width is 23 MHz. I attached the corner simulation result here.

(3) What is your Common Mode? the Rail-Rail input will vary Gm.
The VDD of this design is range from 12V to 20V. The typical value is 16V. The common mode input range is GND_1V to VDD-1V.  Yes the Gm is varied, but the compensation is done for maximum Gm case. Do u think i should make input stage has constant Gm?

Thank you so much

Thank you for your reply. It has miller conpensation in the output stage. sorry, it doesnt shows in the attached schematic.  When simulation, phase margin is ok.

Here are my thoughts :-
a) Your common mode loop may be unstable. This cannot be seen using differential mode simulation. Have you simulated your common mode feedback loop ?

b) Have you done a RCC simulation of your block ? An "unwanted" feedback may be causing this oscillation. This is of course layout dependent.

c) Have you tried a transient sim ?

d) I guess everyone has mentioned that the oscillation is probably causing the rise in current consumption.

e) Does the oscillation occur over the whole range of VDD ?

e) What about your bias circuit. could that be under performing causing an error in your op-amp bias resulting in oscillation ?

f) Your tools do not look like Spectre/Eldo ... could there be a modelling/simulation issue ?

Thank you Harpoon.

Here are my answers :-

a) Your common mode loop may be unstable. This cannot be seen using differential mode simulation. Have you simulated your common mode feedback loop ?

There is not CMFB loop in this circuit. The simulated common mode rejection ratio is 150 dB

b) Have you done a RCC simulation of your block ? An "unwanted" feedback may be causing this oscillation. This is of course layout dependent.
Could you please explain more about RCC simulation? Does it mean, after layout, when we extract our layout for post simulation, we choose RCC mode?

c) Have you tried a transient sim ?
Yes. It is ok for transient.

d) I guess everyone has mentioned that the oscillation is probably causing the rise in current consumption.
U mean because of the oscillation, the current consumption is increase, right?  I guess because of the biasing voltage for last stage transistor is wrong, so the current consumption is increased a lot, and then it osccilates.


e) Does the oscillation occur over the whole range of VDD ?
The VDD could range from 12 to 20V. The above simulation shows under 16V.  I did not sweep the VDD

e) What about your bias circuit. could that be under performing causing an error in your op-amp bias resulting in oscillation ?
I think you are right. The current consumption is dorminated by last stage, M25 and M26. So the biasing for them are very important, which is source voltage of M20 and M19.  I guess because of this bias voltage are wrong, so the current consumption increase a lot.  How to make them stable is the difficult part.  If we can make them stable, i think the current will not change

f) Your tools do not look like Spectre/Eldo ... could there be a modelling/simulation issue ?
I use candence ^^

Hi,

I have designed similar op-amps but they have always been differential output ... hence that was why I suggested cmfb being the problem. You correctly pointed out that there is no cmfb.

Here is a followup ...
B) rcc sim. Do this after layout. If you can see spikes in your ac loop response, then it may explain what u see in real life. Rcc is the closest to real life, but may be slow. Cc sim is the next best thing here ...
C) transient sim. Try a pulse input ... See if the output decays properly. Sim for a long time if possible ... E.g. 10us or so to see if any osc builds up.
E) I meant try changing the bench supply voltage in the real chip and see if the osc occurs.

g) what is the osc frequency observed in the lab? do all parts osc ?
H) looking at yr process, you may need to check what bond pads you are using and more importantly what esd structures you have on that pad. Put those items in yr sim and see how much degradation in phase margin you get.

Lex wrote on Aug 31^st, 2011, 11:47pm:



Rail to rail op amps like this have got to be gain and phase margin tested in three different input biases - high/center/low common mode voltages.

All three have different gain/phase characteristics due to the nature of the input diff pairs bias.

Also, where is the common mode feedback system for the bias?

IMO everyone needs to back up a bit and look for clues in the silicon and then verify with simulations instead of vice versa. I'm suspecting the output stage has more current than planned - this topology can have that problem. It could be from mismatch in the M19, M23, M24 and M26 loop (or the PMOS equivalent), or lower output impedance than anticipated in the output devices.

You should be able to do some tests to determine if that is the case. First, get it in a condition where it isn't oscillating. Hopefully this will happen if you move the common mode input out of center.

1) Check Idd vs Iload. If it is the output stage it should match the simulation when your load debiases the output device that isn't providing current. From this you should be able to determine if it is the output stage.

2) Is the Idd condition sensitive to power supply or the opamp output voltage?

3) Is Idd sensitive to the common mode value of the input?

The second thing I would suspect is your bias circuit. How are you biasing the amp? Beta multipliers can be very sensitive to mismatch.

4) How is the bandwidth? If it is too high then your input stage bias current might be too much.

As far as oscillation is concerned, (I think you want to figure out the Idd first), we need more info. Does the Idd error go away when it isn't oscillating? Is the bandwidth what you expect? What is the frequency of oscillation? Does it change with load current? What are your feedback and capacitive load conditions? Are the pins bonded out? Are you including parasitic caps in your simulation (especially at the inverting node and a distributed cap along the length of the feedback resistor)? How about the bottom plate of your compensation cap? How about the capacitance of the scope probe? (You wouldn't be the first.) But before you start playing with the oscillation problem spend some time with the Idd problem.

Changing temperature can also provide clues. Does putting freeze spray on it solve the problem?

In other words, start monkeying with the silicon and note the funnies. Write down the funnies and the magnitude of the funny . If you can see two or three unusual sensitivities of the problem (i.e. power supply sensitivity) you can usually piece together the problem and verify with simulations. You have the real thing in front of you so you shouldn't be searching for the clues in the simulations - use the real thing. JMO anyway.

Best,
Rob