Hi Designers' Guid Fellow Members:

I have a question about the transistor (CMOS) noise factor Gamma modeling in TSMC technologies.

For a long time I always trust these models from TSMC and managed to get decent simulation/silicon correlation on 180nm/90nm/65nm on VCO design.

However, I recently read about a few papers claiming that gamma is not well modeled and can go higher than 2-3 in real silicon, instead of 0.7 in text books.

I'm wondering that what kind of gamma did TSMC used in their device model and how well are they correlated with silicon in different technologies?