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The Designer's Guide Community Forum › Other CAD Tools › Physical Verification, Extraction and Analysis › layout to schematic problem
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layout to schematic problem (Read 2822 times)
lanfird
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layout to schematic problem
Sep 26th, 2011, 11:56pm  
If I want to use parasitic capacitors of layout instead of mimcap offered by the process, how should I pass LVS? The problem is that when I extract layout capacitor to schematic capacitor (which is a capacitor not provided by the process), I could't get LVS passed.
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ywguo
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Re: layout to schematic problem
Reply #1 - Sep 30th, 2011, 7:30am  
What do you mean by parasitic caps? What is the structure? Generally I think you need SPICE model, and LVS model for it. It is better that there is a pcell.
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