HI ,
Im trying to model  a sin wave generator. And seems nothing is  out  from the  waveform. Copied my testbench and verilog. Do give me your opinion. Appreciate a lot. Thanks

Testbench


module tb_test_ver();   //testbench  module  name

wire  pina, pinb;    // declaring wire input
sine_wave out2(.wave(pinb));
initial $vcdpluson;  //log on vpd file for dve
initial      #(50000000000) $finish;  //set to run for 50,000ps
endmodule


Verilog code  for  sine wave generator

module  sine_wave (wave);

output wave;
real offset;
electrical wave;

parameter real freq   = 1000 from (0:inf);
parameter real ampl= 1;
           
analog begin
  V(wave) <+ ampl * sin(3.142* freq * $abstime);
  $bound_step(0.05/freq);
end
endmodule

Yes, Boe. Thanks for explaining the mistakes. I fix my  verilog and it can can run.

Heres the code. And im running on DVE, this is a part of the  VCS  system at my company.


module  sine_wave (wave);

output wave;
real offset;
electrical wave;

parameter real freq   = 1G;
parameter real ampl= 1;
           
analog begin
  V(wave) <+ ampl * sin(3.142* freq * $abstime);
  $bound_step(0.00001/freq);
end
endmodule

Zahrein,
Note that in the analog section of Verilog-AMS code the units are given in the include file disciplines.vams, usually Volt, Ampere, second, .... And the timescale directive has no effect for the analog stuff.
This is the reason for the $bound_step issue Ken pointed out.
B O E

BTW, it should be 2π (`M_TWO_PI).
-B O E