manikandan
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Posts: 7
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hi, this is a divider verilog a code from designers guide
module divider (out, in);
output out; voltage out; // output input in; voltage in; // input (edge triggered) parameter real vh=+1; // output voltage in high state parameter real vl=-1; // output voltage in low state parameter real vth=(vh+vl)/2; // threshold voltage at input parameter integer ratio=10 from [10:inf); // divide ratio parameter integer dir=1 from [-1:1] exclude 0; // dir=1 for positive edge trigger // dir=-1 for negative edge trigger parameter real tt=1n from (0:inf); // transition time of output signal parameter real td=1n from (0:inf); // average delay from input to output parameter real jitter=0 from [0:td/5); // edge-to-edge jitter parameter real ttol=1p from (0:td/5); // time tolerance, recommend ttol << jitter integer count, n, seed; real dt;
analog begin @(initial_step) seed = -311; @(cross(V(in) - vth, dir, ttol)) begin count = count + 1; // count input transitions if (count >= ratio) count = 0; n = (2*count >= ratio); dt = jitter*$rdist_normal(seed,0,1); // add jitter end V(out) <+ transition(n ? vh : vl, td+dt, tt); end endmodule
What should be the values of jitter and ttot to visualize the effect of jitter? What analysis should i be running in spectreRF to understand jitter?for example, say input is 10MHz and output is 1 MHz.
regards mani
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