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How to predict the reference spur before PLL design (Read 5061 times)
lonemy
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hefei anhui china
How to predict the reference spur before PLL design
Nov 03rd, 2011, 10:34pm
 
Hello everyone:

       We can predict PLL phase noise before PLL circuit design, but how can we predict the reference spur?

Thanks~
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raja.cedt
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Re: How to predict the reference spur before PLL design
Reply #1 - Nov 4th, 2011, 2:52am
 
hello,
When you can predict phase noise why can't for reference spur?
Mainly Cp mismatch, filter oder and Kvco will impact reference spurs (when you have clean supply for CP it's okay to think about only reference spurs but when you have some ripple upon the supply you get some supply spurs), So please check mismatch in CP, roughly calculate and run loop simulation. better use ideal divider and if posb use ideal vco so that you can estimate fastly.

Thanks,
raj.
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rajkumar palwai
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Re: How to predict the reference spur before PLL design
Reply #2 - Nov 4th, 2011, 9:01am
 
lonemy,
Reference spurs are mainly caused by the charge pump leakage and mismatch currents. Charge pump mismatch curents are mainly caused by the process mismatches and finite o/p impedances of charge pumps. You can have a rough idea of their typical values and then calculate the ref spurs power level. Similarly, in any technology u will have some idea about the leakage currents and u can calculate spur because of it.

This article will help u in calculations
"design of high performance charge pumps in phase locked loops" by woogeun rhee
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lonemy
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hefei anhui china
Re: How to predict the reference spur before PLL design
Reply #3 - Nov 5th, 2011, 2:08am
 
Dear All:

     Thank you very much. I use behavior PLL model and set the CP up/down current different based on real ckt Monte Carlo simulation, then I FFT the VCO output waveform, so I think I can get the reference spur.
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