Designer’s Guide Community

‹ Previous topic | Next topic ›

Pages: 1

PLL loop parameters (Read 3807 times)

pumba007

New Member

Offline

Posts: 4

PLL loop parameters
Nov 05^th, 2011, 9:51am

Hi,

I am running a PLL with individual block coded in verilog A.

ref = 104MHz
divider ratio = 28
vco output = 2.912 GHz

What should be the cutoff frequency of the Low pass filter which immediately follows the charge pump which pumps or sucks 100mA.

can somebody explain the relation between chargepump current, filter cutoff and settling time of the PLL. Volatge 0 to 1.

Thanks and regards
manikandan

IP Logged

raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: PLL loop parameters Reply #1 - Nov 5^th, 2011, 11:16am hello, could you please elobarate your question more? What do you mean by cuffof frequency? may be you are intersted to calculte loop filters parameters like Icp,R1,C1,C2. you can chose your Pll BW <10.4Meg, so for this use simple expressions to find all components. Thanks, raj.
Back to top	IP Logged

pumba007 New Member Offline Posts: 4	Re: PLL loop parameters Reply #2 - Nov 5^th, 2011, 11:40am Hi, i was talking about the low pass filter cutoff frequency used to calculate c1, c2 and r. i remember reading from somewhere that this frequency is usually about 1/20 of the reference frequency..is that right? thanks manikandan
Back to top	IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: PLL loop parameters Reply #3 - Nov 5^th, 2011, 1:14pm THis is in a bunch of textbooks on PLL's and control system theory. Online: www.freescale.com/files/rf_if/doc/app_note/AN535.pdf www.ti.com/lit/an/swra029/swra029.pdf and others...
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

Pages: 1

‹ Previous topic | Next topic ›