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rfmagic

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CMOS Passive Mixer
Nov 09^th, 2011, 12:46pm

Hi,

I am analyzing a double balanced cmos passive mixer and I cant really understand the results:
1. the conversion gain that I simulate is -1dB while I would expect it to be -4dB (with a 50% square wave LO)
2. The LO to the mixer is generated by a pulse shaper which generates a 25% duty cycle wave. I would expect that the conversion gain with a 25% duty cycle will be lower than the 50% square wave LO. is this correct?

I appreciate if someone could recommend a good reference which analyzes a passive mixer conversion gain preferably in cmos.

Thanks

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: CMOS Passive Mixer Reply #1 - Nov 10^th, 2011, 1:37am hello, 1.May be you have to consider Switch resistance as well. 2. Yes, with less duty cycle your fundametal harmonic wil go down and all other harmonics will go high, so as far as conversion gain concern 1st harmonic matters. You can refere TH lee RF design book for this topic. Thanks, raj.
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rfmagic

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Re: CMOS Passive Mixer
Reply #2 - Nov 10^th, 2011, 7:37am

The mixers topic in TH Lee book is very limited and does not discuss this scenario.
however I did find old discussions in this forum that have mentioned a very nice paper "A 12-mW Wide Dynamic Range CMOS A 12-mW Wide Dynamic Range CMOS" which discusses various scenarios where the LO signal is square LO or sinusoidal and in a very extreme case the conversion gain can reach 0dB theoretically, but I think that this is not my case where I use only a double balanced CMOS mixer with 25% duty cycle square wave

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: CMOS Passive Mixer Reply #3 - Nov 10^th, 2011, 10:51am Suggest - start out with an all ideal system and go from there. Ideal switches, ideal control signals, etc.
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rfmagic Community Member Offline Posts: 64	Re: CMOS Passive Mixer Reply #4 - Nov 10^th, 2011, 1:41pm Hi loose-electron, I did this experiment and found that the famous -4dB is true for the the ideal case with resistive load to the mixer. however, things gets really complex when there is a capacitive load. The mathematical treatment in the paper that I mentioned is very complex and I am looking for a bit simpler analysis.
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RFICDUDE

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Re: CMOS Passive Mixer
Reply #5 - Nov 10^th, 2011, 7:58pm

There are a number of rather detailed treatments of non-50% duty cycle mixers that were published over the past 1-2 years. Most are fairly deep on the mathematics.

Mirzaei, A.; Darabi, H.; , "Analysis of Imperfections on Performance of 4-Phase Passive-Mixer-Based High-Q Bandpass Filters in SAW-Less Receivers," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.58, no.5, pp.879-892, May 2011

Andrews, C.; Molnar, A.C.; , "A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface," Solid-State Circuits, IEEE Journal of , vol.45, no.12, pp.2696-2708, Dec. 2010

Mirzaei, A.; Darabi, H.; Leete, J.C.; Yuyu Chang; , "Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.57, no.9, pp.2353-2366, Sept. 2010

Andrews, C.; Molnar, A.C.; , "Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.57, no.12, pp.3092-3103, Dec. 2010

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loose-electron

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Re: CMOS Passive Mixer
Reply #6 - Nov 11^th, 2011, 10:10am

rfmagic wrote on Nov 10^th, 2011, 1:41pm:

Hi loose-electron,

I did this experiment and found that the famous -4dB is true for the the ideal case with resistive load to the mixer. however, things gets really complex when there is a capacitive load. The mathematical treatment in the paper that I mentioned is very complex and I am looking for a bit simpler analysis.

Trying to do the math manually for the device in a non ideal system is going to be be difficult (or at least a lot of work to get an approximate answer) What are you trying to achieve here?

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aaron_do

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Re: CMOS Passive Mixer
Reply #7 - Nov 11^th, 2011, 7:39pm

Hi,

If i remember correctly, reducing the duty cycle is a tradeoff between gain and bandwidth. Low duty cycle results in higher conversion gain with the maximum theoretical value of 0 dB. However, as you reduce the duty cycle, the output resistance increases (at the fundamental) causing a reduction in the output bandwidth.

Anyway as for the gain think of it this way.

1) A square wave is a convolution of a square pulse, and an impulse train.

2) A square pulse is a Sinc function in the frequency domain, while an impulse train is still an impulse train at multiples of the LO frequency.

3) So the LO is equivalent to a multiplication of a Sinc function and the impulse train in the frequency domain.

4) The lower the duty cycle, the wider the Sinc function and hence the higher the conversion gain at the fundamental frequency.

5) Also note that you can see the sideband mixing from this picture too...

hope it helps,
Aaron

EDIT

BTW, I find that the best treatment on this subject is still in the book By Stephen A. Mass. Something about Nonlinear RF Analysis...i'll post if i remember.

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rfmagic

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Re: CMOS Passive Mixer
Reply #8 - Nov 13^th, 2011, 11:42pm

Hi aaron_do,

Actually the conversion gain with 25% duty cycle is lower at the fundamental by sqrt(2) than the 50% case. The Fourier series of the 25% duty cycle rectangle waveform (or even less than 25%) shows that amplitude of the fundamental is reduced proportionally with the lower duty cycle. moreover, the 50% case is very attractive to use as it suppresses the even harmonics and also have higher fundamental amplitude.

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aaron_do

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Re: CMOS Passive Mixer
Reply #9 - Nov 14^th, 2011, 12:54am

Hi rfmagic,

Quote:

Actually the conversion gain with 25% duty cycle is lower at the fundamental by sqrt(2) than the 50% case.

Are you talking about capacitive loading? Is this a simulation result or theory? Acutally if you setup your simulation correctly and are using capacitive loading, both theory and simulation will show lower duty cycle gives higher conversion gain. Also what IF are you checking at. As I said there's a bandwidth tradeoff, so you should check both the DC gain (i.e. use a very low IF) and the bandwidth (the IF bandwidth).

Quote:

The Fourier series of the 25% duty cycle rectangle waveform (or even less than 25%) shows that amplitude of the fundamental is reduced proportionally with the lower duty cycle.

Do you mean a periodic waveform? You can see it easier if you split it into the pulse train and the rectangle wave. For the rectangle wave, the duty cycle of course has no meaning, and we are only interested in the pulse width. Narrower pulse width results in wider bandwidth. That's why you get higher conversion gain for lower duty cycle. Again, you need to consider the IF bandwidth.

Quote:

the 50% case is very attractive to use as it suppresses the even harmonics and also have higher fundamental amplitude. �

The fundamental amplitude is lower. There are many papers out there to back that up, but I don't have access at the moment. Also, even harmonics generated by the receiver are common-mode so they will be rejected by differential operation anyway. For even harmonics, you only benefit if you receive strong even harmonics at the antenna. But bear in mind that you can adjust the rejected frequency by changing the duty cycle of the LO (second harmonic may not be the one you want to reject).

Lastly, I have assumed you are talking about a capacitive load.

regards,
Aaron

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rfmagic Community Member Offline Posts: 64	Re: CMOS Passive Mixer Reply #10 - Nov 14^th, 2011, 4:14am My analysis is true for the case where the load to the passive mixer is resistive. however when the load is a capacitor the conversion gain is has a inverse proportion to the duty cycle just as aaron-do has mentioned.
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: CMOS Passive Mixer Reply #11 - Nov 14^th, 2011, 9:59am What are you trying to achieve by making this analysis? Is this purely an academic exercise?
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rfmagic Community Member Offline Posts: 64	Re: CMOS Passive Mixer Reply #12 - Nov 14^th, 2011, 9:52pm Hi loose-electron, I am analyzing a system that is actually working but should be optimized, but as part of the design process I am trying to understand the conversion gain and LO duty cycle trade-offs as I dont see it intuitively.
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rfmagic Community Member Offline Posts: 64	Re: CMOS Passive Mixer Reply #13 - Nov 14^th, 2011, 10:41pm aaron_do, Thanks for the detailed explanation, it really fits the simulation results. Can you explain the difference between resistive load and capacitive load in this application and why the behavior is completely different between the 2 cases? Thanks
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aaron_do

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Re: CMOS Passive Mixer
Reply #14 - Nov 14^th, 2011, 11:03pm

Hi rfmagic,

Sticking to the capacitive loading case, I suppose I can offer one intuitive way to look at it (I think its right but correct me otherwise). This is a time-domain analysis.

1) When you multiply the RF signal by a square wave, you need to look at the part where the square wave is high, and how it overlaps with the RF signal. Assume the RF signal is a sine wave.

2) The peak of the low frequency IF signal occurs when the peak of the RF signal is exactly overlapping with the center of the square wave, and this happens every 1/f_IF seconds (f_IF is the IF frequency).

3) If the overlapping region is very small (very low duty cycle), then you are only capturing the exact peak of the RF signal and it therefore corresponds to a gain of 1.

4) If the overlapping region is large (50% duty cycle for example), then you are capturing a larger section of the sine wave, and the average signal level is smaller.

5) The caveat is that if you only capture a very small portion of the RF sine wave, then the amount of power that you are capturing is very small. This determines the IF bandwidth.

OK the resistive loading case is different. In point 5 I mentioned that the lower the duty cycle, the less power of the RF signal you capture. If you have a capacitive load, you can still get good conversion gain as long as the IF bandwidth is small. This allows sufficient time to charge and discharge the IF capacitive load. With a resistive load, however, if the output power is small, a low power simply will not generate a large voltage across the load resistor. That is why the conversion gain is higher at 50% duty cycle for the resistive load case.

Aaron

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