Code:module test(
reset, clk, datain, dataout);
input [7:0] datain;
output [7:0] dataout;
input clk, reset;
reg [7:0] rega;
reg [7:0] dataout;
always @ (posedge clk or posedge reset) begin
if( reset ==1'b1) begin
rega <= 8'b0;
dataout <= 8'b0;
end
else begin
rega <=datain;
dataout <= rega;
end
endmodule
May I know what the purpose to use rega<=datain & dataout<=rega?
if datain is 1001 0011, what is the expected output?
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what is the purpose to use rega<=datain & dataout<=rega? (Read 1746 times)