Hi,
I am trying to design an opamp using gm/id methodology described in

MILLER OTA DESIGN USING A DESIGN METHODOLOGY BASED ON THE
GM/ID AND EARLY-VOLTAGE CHARACTERISTICS: DESIGN
CONSIDERATIONS AND EXPERIMENTAL RESULTS by Fernando Paixão Cortes, Sergio Bampi.

I dont know how to find the Early Voltage (VA) of nmos/pmos transistors...

Can someone please help me...?

Thanks a lot in advance....

Vinay

Well-done by loose-electron. For analysis, just calculate the Rout by the slope and multiply by Id.

Look up that Early voltage is not that good for many CMOS processes (like few Volts only). Use large L for large Vea and making good current sources. Even better use cascodes or even active cascodes.

Thank you loose-electron. You are right, early voltage is more of a BJT term.

Following are few sentences from the paper I mentioned earlier.

“In addition to the discussed design method(gm/id methodology), we included an additional optimization in the design phase: choosing the transistor lengths (L) to minimize power. In order to accomplish that, we consider another important characteristic related with the gm/ID curve: the relationship between gm/ID versus VA (the Early Voltage parameter). This relationship is considered as a fundamental device
technology relation that determines the minimum allowable transistor lengths. Once the values of the gm/ID ratio and VA parameter (that is directly related with the transistor output resistance, and consequently with the stage DC gain) are chosen, the L of the transistors can be determined in our methodology.

Considering both characteristics, the design procedure consists in two basic phases. First, the W/L of each transistor is found through the gm/ID vs. ID/(W/L) curve. Then, the transistor lengths (L) are found considering the gm/ID vs. VA curve.”

The authors say, "one can find the transistor length from the graph of gm/id vs Va".

I am looking for a procedure or method that helps me plot gm/id vs va in cadence tool.

Thanks a lot...
vinay

Thank you RobG.

Can you please explain how to extrapolate the curves to find va..?
How is it done using cadence tool.

Thanks a lot..
Vinay

The bias curves shown above can be done as a set of DC sweeps on a transistor.

The graphical results shown can then be used to find the Early Voltage.

Print it on a piece of paper and use a ruler.

Thank you loose-electron.

Vinay

Hi Rob,

the concept of Early voltage is not soo bad for CMOS too  ;) ! Of course Vear is not a constant, but depends on dcOP and length, etc. However, it is still a good criteria, easier to check than the output resistance or so.

To get Id curve vs Vds use in Cadence IS("..."). Use the calculator expression deriv(IS("...")) to get the slope, i.e. dId/dVds=1/Rout.

Vear=Id*Rout

Bye Stephan