hello,
yes you are correct, you have to design in such a way that -ve loopgain > +ve feedback. I also doubt how to make -ve loop strong here but i wanted to tell you that due to higher impedance of the loopfilter +ve feedback wont be stronger because it is parallel with pmos transisters. But i have never seen this kind of CP!!

Thanks,
Raj.

hello buddypoor,
you are correct, but i guess it is a bias ckt for charge pump (he has to seperate loopfilter from this ckt).

I have a doubt here, forget about chargepump action,here how to make -ve feedback stronger?

Thanks,
raj.

buddypoor wrote on Nov 17^th, 2011, 5:42am:


Dear Sir:

       as you told, how can I check the stability of this kind of ckt? thanks

I think this charge pump is only stable above certain switching frequency. If you want to lower the stable frequency, maybe one way is to change the current mirror ratio.

lonemy wrote on Nov 17^th, 2011, 5:03am:


The loops do not look like they interact to me - just make sure that loop1 is stable to start with. Loop 2 is positive, but don't look at it's DC gain or small signal critera - pure positive feedback won't make an oscillator - it will just force the output to a rail. Don't worry about it -- the system should be designed around this circuit to prevent it from sticking at a rail.  

You need to look at the stability of the *system*. The stability of the system is determined by how long the switch is on and the time constant of the LPF - look at the voltage change at the LFP when the switch is turned on for "dT" seconds. It will change dV = Idc/C*dT. Yes, Idc has a small dependance on the current output (i.e. positive feedback additional current from ro2) but the contribution of ro2 will be small. Even if it is not, you are only worried about the amount of dV, not how you got it. You can do a discrete time analysis and check the stability of the *system* but it doesn't have much to do with the positive feedback in loop2.

The instability you want to avoid is having the LPF jump rail to rail with each update. You prevent that by limiting the maximum charge time and/or making the cap large enough to prevent a large jump. I doubt you will have to worry about this as I'm positive that the settling requirements for the PLL itself will impose far more restrictive conditions to ensure stability.

I think it would be an order of magnitude increase in signal dependent U/D matching even with opamp imperfections, but as you noted it may not improve the overall performance of the PLL loop. FWIW, the circuit in the paper is slighter different.

rg

ece.wpi.edu/analog/resources/PLLTutorialISSCC2004.pdf

see page 50 of the above