To be more clear, this is the signal train I want to have :


[img][/img]

How can I obtain that output ?
Thank you for your help,
ssp

Hi Ken,

the problem is that my code doesn't generate the output pulse as I wich it did. It seems that the @cross function is not working well, or perhaps the code I made have a mistake in it that I can't detect...I don't know if this can help but my input signal comes from a dynamic comparator working with an intern clock of 12ns period. I want to use the output pulse as a reset signal for a PMOS transistor.

Hi,

Your cross event tests for negative crossing with threshold 0. This is probably not what you intended.

- B O E

By reading verilog-ams guide more carefully, I only need to add V(in)-1 in the cross function to make it work:

@(cross(V(in)-1,-1))

Hi guys,

I still don't exactly get the result I'm expecting with this code:

Code:

module allo(in,out);
parameter real td = 10n;   // width of pulse
parameter real tt = 0n;	// output transition time (s)
parameter real t1 = 0n;

   output out;
   input in;
   voltage in, out;

   real Vout, tend,rst;

analog begin

	@ (initial_step or cross(V(in)-1, -1)) begin
	   // @ (cross(V(in)-1, -1)) begin
		 Vout = 0;
		 tend = $abstime + td;//return simulation time + td
	  end

	  @(timer(tend))
		 Vout = 1.8;
		 V(out) <+ transition(Vout, td, tt);
	   end

endmodule
 

I want to detect the first falling edge on the Vin signal (time 65.24ns), while my code only detects the second falling edge at time 75.21 ns. Why is that ? Is there a way I can fix my code to detect the first falling edge ?

Thanks for your help,
ssp

ssp wrote on Nov 23^rd, 2011, 3:06pm:
You do detect the edge @ 65.24 ns; because of the 10 ns delay you specified (td in transition filter), the output changes @ 75.24.

BTW, Ken: The contribution statement is not inside the @ block, the code is just poorly indented.

- B O E

Argh. Normally I will not answer questions from people that cannot be bothered to format their code in a readable fashion. I should have stuck with that policy here.

Code:

module allo(in,out);
parameter real td = 10n;   // width of pulse
parameter real tt = 0n;	// output transition time (s)
parameter real t1 = 0n;
output out;
input in;
voltage in, out;
real Vout, tend,rst;

analog begin
    @(initial_step or cross(V(in)-1, -1)) begin
	  Vout = 0;
	  tend = $abstime + td;//return simulation time + td
    end

    @(timer(tend))
	  Vout = 1.8;

    V(out) <+ transition(Vout, td, tt);
end
endmodule 

Improperly indented code is largely unreadable, leading to confusion and mistakes, and making it hard for people to help you. Before asking someone to look at your code, you should indent it properly. It only took me a few seconds to do it, and in doing it you often find the problem yourself.

-Ken