Stephan,

  My feeling is that this is more of a perception issue than an actual
issue. For example, once a customer gave me an ADC testcase
written in Verilog-A. A simple ADC was taking several days to
complete, if it did not fail to converge. A quick look at the models
found the issue. The primitive components were all modeled with if,
then, else statements. For functional simulations, this modeling style
was fine. However, the primitives were being used as analog
components in this particular simulation. So the primitive models
needed to be re-written to have well-behaved analog behavior.
Re-writing the models, the simulation finished in about 20m. So my
thought is that is not so much of an unsolvable technical issue as
the need to create a behavioral model optimized for an application.
Modelers already create multiple model levels to address different
simulation requirements: level0, level1, etc., so this does not seem
to be that radical of a suggestion. The modeling style for periodic
steady-state analysis is well known and documented. There is an
S/H code sample in the switched capacitor white paper and the
D-flip flop example. Another approach that can be useful is to
reduce a block to its components. This works for example when
trying to simulate the R/S flip-flop in a DC-to-DC Converter. While
using the same models for transient analysis and PSS analysis
would be convenient, even for, transient analysis the modeling
style needs to be suited to the application.

                                                          Best Regards,

                                                            Sheldon