Hi RobG and others ,
Here i am attaching my schematics as drawn in cadence..
Iin1 ,Iin2 are all annotated.Also Ibias=3nA is annotated in the below image.Vdd is set to 0.45V and Vss to -0.45V. Iin1=3nA and Iin2=3nA
The vdd is as inout to the FGMOS vs Id is plotted in the below image u can see the nFG7 to 2 are in this ...See left for counting the FGMOS serial number leftmost is nFG1 and so on to right.
Further for the waves of nFG1/D see below
I have also plotted the drain currents in each transistors verses the input current Iin1 from-3nA to 3nA.
See below image for the Iin1 Vs Id of nFG1.
If you find that the circuit should be manipulated ...please let me know where...???
Also The Iin1 Vs Iout from rightmost corner resistor(see schematic)..
is plotted.
Hope u all will suggest me some corrections if they are needed.
and let me know so that it will work as multiplier.
The capacitors used at the FGMOS gate inputs is of value 50pF each.
I have tried the circuit by removing the FGMOS capacitors and the associated ckt to make it purely MOS ckt i am getting the same results almost.