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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: 4-quad current multiplier Reply #15 - Dec 09^th, 2011, 5:44pm If hes at 3nA bias current, I want to see where he is on the bias curve of the device. The circuit was spaghetti, I agree.
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muffassir

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Re: 4-quad current multiplier
Reply #16 - Dec 10^th, 2011, 5:54am

Hi RobG and others ,

Here i am attaching my schematics as drawn in cadence..

Iin1 ,Iin2 are all annotated.Also Ibias=3nA is annotated in the below image.Vdd is set to 0.45V and Vss to -0.45V. Iin1=3nA and Iin2=3nA

The vdd is as inout to the FGMOS vs Id is plotted in the below image u can see the nFG7 to 2 are in this ...See left for counting the FGMOS serial number leftmost is nFG1 and so on to right.

Further for the waves of nFG1/D see below

I have also plotted the drain currents in each transistors verses the input current Iin1 from-3nA to 3nA.

See below image for the Iin1 Vs Id of nFG1.

If you find that the circuit should be manipulated ...please let me know where...???

Also The Iin1 Vs Iout from rightmost corner resistor(see schematic)..
is plotted.

Hope u all will suggest me some corrections if they are needed.
and let me know so that it will work as multiplier.
The capacitors used at the FGMOS gate inputs is of value 50pF each.

I have tried the circuit by removing the FGMOS capacitors and the associated ckt to make it purely MOS ckt i am getting the same results almost.

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RobG

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Re: 4-quad current multiplier
Reply #17 - Dec 10^th, 2011, 6:38am

what paper is this based on? I still don't see how it can be anything but a mirror, but I remember a paper by Hassler that also confused me.

You should be able to plot that schematic as a postscript file and then convert it to pdf using ps2pdf. If you attach that instead of the screen shot it might help us as the screen shot is too small.

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Vladislav D Community Member Offline Posts: 76 The Netherlands	Re: 4-quad current multiplier Reply #18 - Dec 10^th, 2011, 9:05am Dude.... are there capacitors ? the gates are floating.....you d'better to connect the gates to something....
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Vladislav D Community Member Offline Posts: 76 The Netherlands	Re: 4-quad current multiplier Reply #19 - Dec 10^th, 2011, 9:07am Ask yourself what is the voltage at the gates at DC ? There is no DC path for the input current. I'd suggest to start from a one-gate MOS and to get rid from the current mirrors that copying bias current. Who knows if transistors are in saturation there....and of course, capacitors should not be there
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: 4-quad current multiplier Reply #20 - Dec 10^th, 2011, 9:44am One more time: Where are you on the bias curves for the transistors in the system? The reason I am asking this question: You will learn something if you go answer this question first. Your DC bias situation needs to be resolved first, if the circuit architecture is not correct the bias will not be correct. Hint! Hint!
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RobG

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Re: 4-quad current multiplier
Reply #21 - Dec 10^th, 2011, 7:43pm

Vladislav D wrote on Dec 10^th, 2011, 9:05am:

Dude.... �are there capacitors

? the gates are floating.....you d'better to connect the gates to something....

Vlad - The capacitors are floating gate capacitors so that is ok.

I think I'm catching on to how this works. There are two floating gates, so that means the gate voltage of the MOS is the sum of the voltages at the floating gate terminals. Thus Vgs ~ exp(Vgs1+Vgs2) which is what you need to multiplying action. At least I think so...

rg

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Vladislav D

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Re: 4-quad current multiplier
Reply #22 - Dec 11^th, 2011, 6:41am

RobG wrote on Dec 10^th, 2011, 7:43pm:

Vladislav D wrote on Dec 10^th, 2011, 9:05am:

Dude.... �are there capacitors

? the gates are floating.....you d'better to connect the gates to something....

Vlad - The capacitors are floating gate capacitors so that is ok.

OK. I got it. However, there is still a question how does a simulator interpret the potential at the gates at DC.
Muffassir, have u tried transient analysis? Also, I'd still recommend to get rid from current mirrors which copy Ibias for debugging purpose.

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loose-electron

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Re: 4-quad current multiplier
Reply #23 - Dec 11^th, 2011, 11:38am

You have devices that have no DC bias.

Your definition of DC bias points has not been done with respect to transistor transfer curves.

The static currents are so small that they are probably below the valid bias points of the models, or under the error tolerance settings of the simulator.

Go resolve your DC bias situation first.

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muffassir

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Re: 4-quad current multiplier
Reply #24 - Dec 14^th, 2011, 3:58am

RobG wrote on Dec 10^th, 2011, 6:38am:

what paper is this based on? I still don't see how it can be anything but a mirror, but I remember a paper by Hassler that also confused me.

yes u are correct its inspired from the Pual Hassler's paper.

Also i have tried to check the currents through each transistors.I changed the W/L ratios to get the currents in nFG1 and 2 to be Ib using trans analysis..now i am trying to get the Iin2 + Ib in nFG6 and 7 ...i think i am inserting Iin2 at the wrong place as the current is not getting added at the drain of nFG6 .Any suggestion in this regard is much appreciated.
Also i am new to cadence so soon i will upload the pdf file as suggested by you.

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: 4-quad current multiplier Reply #25 - Dec 14^th, 2011, 11:32am Are you familiar with bias curves for transistors or not?
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loose-electron

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Re: 4-quad current multiplier
Reply #26 - Dec 14^th, 2011, 11:36am

RobG wrote on Dec 10^th, 2011, 7:43pm:

Vladislav D wrote on Dec 10^th, 2011, 9:05am:

Dude.... �are there capacitors

? the gates are floating.....you d'better to connect the gates to something....

Vlad - The capacitors are floating gate capacitors so that is ok.

I think I'm catching on to how this works. There are two floating gates, so that means the gate voltage of the MOS is the sum of the voltages at the floating gate terminals. Thus Vgs ~ exp(Vgs1+Vgs2) which is what you need to multiplying action. At least I think so...

rg

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

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RobG

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Re: 4-quad current multiplier
Reply #27 - Dec 14^th, 2011, 12:41pm

loose-electron wrote on Dec 14^th, 2011, 11:36am:

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

They use tunneling to put the proper amount of charge on the gate. In theory this will never leak off so it will maintain. The floating cap pretty much acts like a battery in series with the gate. I've seen circuits published where the idea is used to trim opamp offsets or even provide voltage references. I (and others) have a hard time believing that the charge will remain constant over long periods of time, especially for commercial products that can't fail in the field after a year, but Hassler and others swear it will.

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loose-electron

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Re: 4-quad current multiplier
Reply #28 - Dec 14^th, 2011, 4:36pm

RobG wrote on Dec 14^th, 2011, 12:41pm:

loose-electron wrote on Dec 14^th, 2011, 11:36am:

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

They use tunneling to put the proper amount of charge on the gate. In theory this will never leak off so it will maintain. The floating cap pretty much acts like a battery in series with the gate. I've seen circuits published where the idea is used to trim opamp offsets or even provide voltage references. I (and others) have a hard time believing that the charge will remain constant over long periods of time, especially for commercial products that can't fail in the field after a year, but Hassler and others swear it will.

They may swear by it, but the rest of the world will swear at it.

Can't seem to get the OP to look at the bias curve location of things.
If you can not set the bias point up properly, everything else is a failure.
Also, currents stated are below default error tolerance of most simulators,
so I think hes looking at nonsense.
I tried.

Anybody got a PDF of this Hassler paper they can send me or post here?

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muffassir Junior Member Offline Posts: 13 Planet Earth	Re: 4-quad current multiplier Reply #29 - Dec 15^th, 2011, 12:20am Hi all, Well below is the paper i am implementing.Usually FGMOS papers are all influenced by the basic work carried out by P.Hasler,C.Driorio,C.Mead at Caltech. As said by RobG they use the tunneling concept. It seems that the RobG is familiar with the FGMOS . The paper is in 350nm tech..and i am having 180nm tech..
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